A COMPARATIVE REVIEW OF FPGA AND GPU ACCELERATORS FOR AI

Аннотация

This investigation presents a brief yet thorough comparative assessment of FPGA (SoC)– based and GPU-based AI accelerators across applications that encompass edge devices to data center training environments. Primary performance parameters—latency, throughput, energy efficiency, programmability, and scalability—are thoroughly evaluated with a specific concentration on deep neural network inference and training. The research further highlights the significance of hardware/software co-design and high-level synthesis (HLS) in augmenting FPGA performance. Representative platforms, such as the one from Xilinx and Nvidia, are referenced to illustrate prevailing trends. Findings suggest that while GPUs excel in throughput and development simplicity, FPGAs exhibit reduced latency and enhanced energy efficiency in power-sensitive or real-time applications. Keywords: FPGA; GPU; AI accelerator; edge computing; deep neural networks; latency; energy efficiency; hardware/software co-design; high-level synthesis. 1. Introduction The rapid advancement in artificial intelligence has driven a transformative evolution in computing architectures, resulting in the emergence of specialized hardware accelerators tailored to diverse application domains. Traditional central processing units (CPUs) are increasingly inadequate for the computational and energy demands of deep neural network (DNN) training and inference, leading to the rise of accelerators such as Graphics Processing Units (GPUs) and Field-Programmable Gate Arrays (FPGAs). GPUs have become the standard for large-scale AI applications due to their ability to perform massively parallel computations, supported by robust programming ecosystems and libraries like CUDA and cuDNN that have been refined over decades [1]. Their capability to process thousands of threads concurrently makes them ideally suited for training deep neural networks, where high throughput and large- scale data processing are paramount. Alternatively, Field-Programmable Gate Arrays (FPGAs) present a valuable benefit attributed to their innate versatility and ability to be reconfigured, which permits creators to construct personalized hardware systems that can be thoroughly refined for unique duties. This level of customization engenders deterministic processing with ultra-low latency and enhanced energy efficiency—attributes that are especially critical in environments constrained by power and necessitating real-time performance, such as edge computing devices, autonomous systems, and Internet of Things (IoT) applications [2]. In contrast to Graphics Processing Units (GPUs), whose architectures remain static and are optimized for a wide array of operations, 68 YOSH OLIMLAR ILMIY-AMALIY KONFERENSIYASI in-academy.uz/index.php/yo FPGAs facilitate hardware/software co-design wherein both the algorithm and its corresponding hardware implementation are concurrently optimized. This paradigm fosters applications capable of functioning with minimal power expenditure while still adhering to stringent performance criteria. A notable difference arises between GPUs and FPGAs, especially as we evaluate key platforms like the NVIDIA A100 GPU and the Xilinx Zynq UltraScale+ System on Chip (SoC) FPGA. The NVIDIA A100, equipped with its sophisticated tensor cores and elevated memory bandwidth, is meticulously engineered to achieve exceptional throughput for data center training tasks. It accommodates mixed-precision computing and scales effectively across multi- GPU clusters, rendering it a preferred option for cloud-based deep learning applications. Conversely, the Xilinx Zynq UltraScale+ platform epitomizes the FPGA paradigm by amalgamating both programmable logic and processing system cores within a singular chip. This synthesis facilitates the creation of application-specific accelerators that attain low latency and high energy efficiency—characteristics that are fundamental for edge inference applications where real-time responsiveness is paramount [1], [3]. Recent scholarly literature has delved into these distinctions with considerable depth. Investigations have indicated that while GPUs are proficient in contexts requiring high- throughput processing and expedited development cycles, they often exhibit elevated latency and energy consumption as a result of intrinsic architectural overheads and dependency on batch processing. In contrast, FPGAs, despite traditionally presenting greater programming challenges, have exhibited substantial advantages in energy efficiency and latency mitigation when optimized through high-level synthesis (HLS) methodologies [3], [4]. This emerging trend of utilizing high-level synthesis (HLS) to bridge the programmability gap is revolutionizing the integration of FPGAs within artificial intelligence systems, thus making them more attainable for developers who may lack advanced hardware design expertise. The purpose of this investigation is to deliver an extensive review of these two ac