Integrating Power-Saving Techniques into Design for Testability of Semiconductors for Power-Efficient Testing

Аннотация

This article addresses the issue of improving CITATION energy efficiency in the testing of system-on-chip (SoC) semiconductor systems, including heterogeneous Vijayaprabhuvel Rajavel. (2025). Integrating Power-Saving Techniques into Design for Testability of Semiconductors for Power-Efficient Testing. The computing cores and AI accelerators. An analysis of SoC American Journal of Engineering and Technology, 243–251. architecture and existing Design for Testability (DFT) https://doi.org/10.37547/tajet/Volume07Issue03-22 methodologies is presented, considering energy-saving COPYRIGHT techniques such as clock gating, power gating, and © 2025 Original content from this work may be used under the terms dynamic voltage and frequency scaling (DVFS). A of the creative commons attributes 4.0 License. literature review highlights the insufficient development of a comprehensive approach to reducing power consumption specifically during testing procedures. Practical examples, including Qualcomm Snapdragon, Apple A-Series, and Tesla FSD, demonstrate that integrating low-power techniques into DFT can significantly reduce energy consumption (by an average of 20–35%) without compromising test coverage quality. The proposed analysis confirms the effectiveness of combining traditional scan chains, built-in self-test (BIST), and boundary scan with power management mechanisms, contributing to reduced thermal loads and increased reliability of modern SoCs in mass production. The findings presented in this article will be of interest to leading researchers and practicing engineers in the fields of microelectronics, materials science, and energy optimization, aiming to integrate advanced testing methodologies with innovative energy-saving solutions to develop reliable, high-performance, and environmentally sustainable semiconductor systems. Keywords: System-on-chip, SoC, Design for Testability (DFT), energy efficiency, clock gating, power gating, DVFS, scan chains, semiconductor testing, power management, AI accelerators. The American Journal of Engineering and Technology 243 https://www.theamericanjournals.com/index.php/tajet The American Journal of Engineering and Technology Introduction: new interdisciplinary approaches. The modern semiconductor industry is characterized by Leelakrishnan S. and Chakrapani A. [2] demonstrate the the rapid integration and increasing complexity of practical implementation of energy-saving techniques system-on-chip (SoC) functionality. This trend is driven in wireless sensor networks through the use of VLSI by the demand for compact, high-performance, and, technologies on FPGA platforms. The work of Marwedel most importantly, energy-efficient solutions across a P. [9] on embedded system design within the wide range of applications, from mobile devices and the framework of cyber-physical systems and the Internet Internet of Things (IoT) to automotive systems and of Things presents a systematic approach to reducing artificial intelligence. Despite extensive research on power consumption, proposing new methodological reducing power consumption during SoC operation, schemes for integrating energy-efficient solutions into energy-saving methodologies remain insufficiently test complexes. explored during the testing phase of semiconductor Jouppi N. P. et al. [6] propose an architecture optimized devices. Testing modes often require higher clock for deep learning, while Sze V. et al. [7] provide a frequencies, parallelism, and repeated activation of detailed review of efficient neural network processing various chip components, leading to increased power methods. Nielsen C. [3] examines the transformation of consumption and potential overheating [1]. laboratory practices in response to rapidly evolving Additionally, the growing demands for performance technological requirements. and scalability in modern SoCs, including The article "Low Power Design for Testability" [10], heterogeneous computing cores (CPU, GPU, AI emphasizes the relevance of implementing energy- accelerators), complicate Design for Testability (DFT) saving measures to prevent overloads during schemes, increasing the risk of failures and economic automated test vector generation. Similarly, Khursheed costs. Therefore, ensuring low power consumption S., Al-Hashimi B. M. [11] discusses strategies that can during testing is a critical challenge in the development adapt to multi voltage designs, enabling energy savings of next-generation SoCs [1]. without compromising test coverage. Shetty S. K., Mohapatra E. [12] focus on the design and testing of LITERATURE REVIEW energy-efficient cache memory, aiming to reduce power consumption without sacrificing test operation Gupta M., Gupta S., and Aswal P. [1] provide a performance. The work of Thota S. et al. [13] addresses comprehensive analysis of the architectures and the application of multi-threshold CMOS technology to applications of modern System-on-Chip designs, ensure high-speed, low-power a