EFFICIENT 64-BIT VEDIC MULTIPLIER DESIGN FOR ENHANCED COMPUTATIONAL SPEED

Аннотация

The demand for high-speed and efficient multipliers is crucial in modern digital systems, especially in applications such as image processing, cryptography, and digital signal processing, where multiplication is a fundamental operation. This paper presents the design and implementation of an efficient 64-bit Vedic multiplier using the Urdhva Tiryakbhyam algorithm, one of the fastest methods derived from ancient Vedic mathematics. The proposed design leverages the parallelism inherent in Vedic multiplication techniques to significantly reduce computation time and improve processing speed. Comparisons with conventional multipliers demonstrate that the Vedic approach achieves a marked increase in performance and efficiency. Simulation results confirm that the 64-bit Vedic multiplier outperforms standard multipliers in terms of speed, resource utilization, and power consumption, making it a suitable candidate for high-performance computing applications.