LOCALIZED OXIDE TRAPPED CHARGE'S EFFECT ON THE CAPACITANCE BETWEEN GATE-SOURCE IN FINFET DEVICES

Аннотация

This study examines the effect of localized oxide trapped charge on the capacitance of the gate-to-source (drain) connection in silicon-on-insulator (SOI) based FinFET devices. The capacitance-voltage characteristics of the gate-source capacitance are analyzed using a small AC signal technique. The gate-source (gate- drain) capacitance is evaluated at various positions along the channel where the localized oxide trapped charge is present. Additionally, the distribution of charge carriers along the channel at different locations of the localized oxide trapped charge is taken into account. The results demonstrate a consistent increase in the gate-source capacitance as the distance between the source-channel boundary and the center of the localized charge increases. Keywords: Capacitance-Voltage (C-V) characteristics, oxide trapped charge, silicon-on-Insulator (SOI), doping level, depletion layer, charge distribution. Introduction. MOSFETs, particularly FinFETs, can experience degradation due to electrical stress or radiation, impacting their performance. Key degradation mechanisms include hot carrier injection, bias temperature instability, off stress, and radiation-induced charge accumulation. These effects result from charges trapped in the oxide layer or at the interface, necessitating careful consideration in the design of analog and digital integrated circuits. Charge trapping in the oxide affects MOSFET parameters such as threshold voltage, subthreshold slope, and transconductance, which lead to performance degradation. To analyze charge trapping mechanisms, it is essential to develop methods for estimating the localization and distribution of trapped charge along the channel. A practical diagnostic approach involves measuring the capacitance-voltage characteristics of lateral source (drain)-channel p-n junctions, as experimentally validated in the literature. Non-uniform charge distribution in the oxide or at the semiconductor-oxide interface is reflected in these junctions, providing insights into charge trapping along the channel. This study adapts this method, originally designed for planar MOSFETs, to SOI FinFETs. It focuses on the influence of oxide and interface-trapped charge on the capacitances of lateral source-channel (drain-channel) p-n junctions. In SOI FinFETs, the gate-source (or gate-drain) connection includes this capacitance (Cp-n), which https://scientific-jl.com/wsrj 1 3 1 Volume-40_Issue-2_June-2025 World scientific research journal significantly contributes to the overall capacitance of the selected connection. The gate-source and gate-drain connections consist of gate oxide capacitance (Cox), depletion layer capacitance (Cdep), and source-channel p-n junction capacitance (Cp- n). In the proposed approach, only the barrier capacitance of the source-channel p-n junction is considered. A positive voltage is applied to the n-type source contact relative to the gate, inducing accumulation near the oxide-semiconductor interface, thereby excluding Cdep. Under these conditions, the resulting capacitance Cgs can be expressed as follows: where Cox is the gate oxide capacitance per unit area, which remains independent of the applied voltage. Estimations indicate that the depletion layer width of the source-channel (drain-channel) p-n junction is approximately 0.1 μ, while the gate oxide thickness tox is 2.5 nm. Consequently, Cp−n is significantly smaller than Cox, leading to: Since Cp−n is highly sensitive to the distribution of trapped charge in the oxide, this study simulates the dependence of Cgs on the position of localized oxide-trapped charge along the channel. Simulation conditions and transistor parameters. 3D simulation was provided by using Advanced TCAD Sentaurus. The C-V dependence of the gate-source (gate- drain) connections was simulated on the basis of the small AC signal method. It is used a 1 MHz frequency in the method. The structure of the simulated SOI FinFET is shown in Fig. 2. Gate length L and gate oxide thickness are 25 nm and 2.5 nm gate respectively. The thicknesses of the channel T and back oxide T are 30 and 100 Si box nm respectively. The width of the channel is 12 nm. The doping level of the p-Si channel is 1·1015 cm-3. https://scientific-jl.com/wsrj 1 3 2 Volume-40_Issue-2_June-2025 World scientific research journal Fig.1. Cross-section of the simulated Fig.2. 3D structure of the simulated SOI FinFET with capacitances between SOI FinFET contacts. The capacitance C of the gate-source connection is simulated at different gs distances between the center of the local oxide trapped charge and source-channel border. Local oxide trapped charge is modeled as a homogeneously charged area in the oxide layer. The density of charge in the charged area is 1012 cm-2 (or 4·1018 cm- 3) and is appropriate to the value which can take place in MOSFET. Linear size of the local charge along channel d=5nm. While the depletion layer width of the lateral source-channel (drain-channel)